This invention relates to the field of electronic signal processing, and more specifically to a digital-to-analog (D/A) converter which digital input comprises two or more digital data streams.
A digital-to-analog converter translates a digital data stream into a corresponding analog signal output. High speed D/A converters are implemented almost exclusively with current steering, due to faster settling and much better dynamic performance.
At very high data rates, the input/output (I/O) interface usually works at a lower rate than the D/A core itself, thus a data multiplexer may be needed before the D/A converter. Several techniques have been proposed to reduce the code dependent errors and noise, that can result in harmonic distortion and spurs in the analog output signal. A conventional solution uses a data multiplexer and a D/A core running at twice the speed of each of the input data rates. However, this solution exhibits code dependent switching. Further, the presence of a high-speed data stream combiner is a drawback. The U.S. Pat. No. 6,768,438 describes a code independent switching technique that can improve the dynamic behavior, using a current steering pair for each data stream, all said steering pairs sharing the same tail current. This solution has the disadvantage of having multiple clock phases, leading to spurious responses. Another technique, described in the U.S. Pat. No. 7,034,733, combines an input data multiplexer with clock-shaping circuitry in order to enhance the dynamic performance, such that two phases of the clock are used. Although the circuit achieves a code independent switching at the current steering node, it appears to have a major drawback in that the actual current switching is determined by the two edges of each of the two said phases of the clock. If the phase clock generator, or the shaping circuitry, or the layout routing, introduce any kind of mismatch between the timing of the two phases of the clock, the dynamic performance will be reduced by a spur at Fsample/2 (half the sampling data rate) and Fsample/2−Fsignal (image of the signal frequency with respect to half of the sampling data rate).
It would be desirable, therefore, to provide a D/A converter section implementation combining the benefits of an input data multiplexer, a code independent switching at the current steering node, and of switching driven by a single phase clock.